`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   09:22:25 11/21/2012
// Design Name:   memoria_juego
// Module Name:   C:/Users/maye/Desktop/taller/barcos/pruebamen.v
// Project Name:  barcos
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: memoria_juego
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module pruebamen;

	// Inputs
	reg clk_i;
	reg [15:0] adre_a_i;
	reg [7:0] adre_b_i;
	wire [2:0] sal_o;
	reg write_i;
	reg [2:0] dato_i;
	reg read_i;

	// Instantiate the Unit Under Test (UUT)
	memoria_juego uut (
		.clk_i(clk_i), 
		.adre_a_i(adre_a_i), 
		.adre_b_i(adre_b_i), 
		.sal_o(sal_o), 
		.write_i(write_i), 
		.dato_i(dato_i), 
		.read_i(read_i)
	);

	always begin
		#50 clk_i=~clk_i;
	end
	initial begin
		// Initialize Inputs
		clk_i = 0;
		adre_a_i = 1;
		adre_b_i = 0;
		write_i = 0;
		dato_i = 4;
		read_i = 0;

		// Wait 100 ns for global reset to finish
		#100;
		write_i=1;
        
		// Add stimulus here

	end
      
endmodule

